Skip to content

Instantly share code, notes, and snippets.

@Yamakaja

Yamakaja/lmk04828b_regmap.json

Last active June 2, 2022 08:57
Show Gist options
  • Save Yamakaja/49d9872d2df84e580aaaa0851d24f838 to your computer and use it in GitHub Desktop.
Save Yamakaja/49d9872d2df84e580aaaa0851d24f838 to your computer and use it in GitHub Desktop.
Download ZIP
Raw
lmk04828b_regmap.json
[
{
"addr": 0,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "RESET",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal operation"
},
{
"value": 1,
"name": "RESET",
"description": "Reset (automatically cleared)"
}
]
}
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SPI_3WIRE_DIS",
"description": "Disable 3-wire SPI mode. 4-wire SPI mode is enabled by selecting SPI Read back in one of the output MUX settings. For example, CLKin0_SEL_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "3-wire mode enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "3-wire mode disabled"
}
]
}
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "constant",
"end": 2,
"start": 2,
"value": 0
},
{
"fieldtype": "constant",
"end": 1,
"start": 1,
"value": 0
},
{
"fieldtype": "constant",
"end": 0,
"start": 0,
"value": 0
}
]
},
{
"addr": 2,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "constant",
"end": 2,
"start": 2,
"value": 0
},
{
"fieldtype": "constant",
"end": 1,
"start": 1,
"value": 0
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "POWERDOWN",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 3,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "ID_DEVICE_TYPE",
"description": "PLL product device type",
"valid": {
"type": "constant",
"value": 6
}
}
]
},
{
"addr": 4,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "ID_PROD[15:8]",
"description": "MSB of the product identifier",
"valid": {
"type": "constant",
"value": 4
}
}
]
},
{
"addr": 5,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "ID_PROD[7:0]",
"description": "LSB of the product identifier",
"valid": {
"type": "constant",
"value": 5
}
}
]
},
{
"addr": 6,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "ID_MASKREV",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NAME",
"description": "Descr"
}
]
}
}
]
},
{
"addr": 12,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "ID_VNDR[15:8]",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NAME",
"description": "Descr"
}
]
}
}
]
},
{
"addr": 13,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "ID_VNDR[7:0]",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NAME",
"description": "Descr"
}
]
}
}
]
},
{
"addr": 256,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout0_1_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout0_1_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout0_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 2,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 257,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout0_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout0_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 259,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout0_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout0_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout0_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 260,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout0_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout1_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout1_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout1_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 261,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout0_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout0_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 262,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout0_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout0_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout0_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout0_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout0_1_PD",
"description": "Powerdown the clock group defined by 0 and 1.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout1_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout1_PD",
"description": "Powerdown SDCLKout0 and set to the state defined by SDCLKout0_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 263,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout1_POL",
"description": "Sets the polarity of clock on SDCLKout1 when device clock output is selected with SDCLKout1_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout1_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout0_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout0_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 264,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout2_3_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout2_3_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout2_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 4,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 265,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout2_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout2_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 267,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout2_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout2_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout2_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 268,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout2_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout3_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout3_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout3_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 269,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout2_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout2_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 270,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout2_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout2_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout2_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout2_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout2_3_PD",
"description": "Powerdown the clock group defined by 2 and 3.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout3_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout3_PD",
"description": "Powerdown SDCLKout2 and set to the state defined by SDCLKout2_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 271,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout3_POL",
"description": "Sets the polarity of clock on SDCLKout3 when device clock output is selected with SDCLKout3_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout3_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout2_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout2_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 272,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout4_5_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout4_5_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout4_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 8,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 273,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout4_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout4_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 275,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout4_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout4_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout4_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 276,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout4_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout5_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout5_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout5_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 277,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout4_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout4_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 278,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout4_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout4_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout4_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout4_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout4_5_PD",
"description": "Powerdown the clock group defined by 4 and 5.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout5_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout5_PD",
"description": "Powerdown SDCLKout4 and set to the state defined by SDCLKout4_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 279,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout5_POL",
"description": "Sets the polarity of clock on SDCLKout5 when device clock output is selected with SDCLKout5_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout5_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout4_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout4_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 280,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout6_7_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout6_7_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout6_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 8,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 281,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout6_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout6_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 283,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout6_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout6_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout6_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 284,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout6_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout7_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout7_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout7_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 285,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout6_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout6_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 286,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout6_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout6_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout6_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout6_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout6_7_PD",
"description": "Powerdown the clock group defined by 6 and 7.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout7_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout7_PD",
"description": "Powerdown SDCLKout6 and set to the state defined by SDCLKout6_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 287,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout7_POL",
"description": "Sets the polarity of clock on SDCLKout7 when device clock output is selected with SDCLKout7_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout7_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout6_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout6_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 288,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout8_9_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout8_9_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout8_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 8,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 289,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout8_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout8_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 291,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout8_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout8_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout8_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 292,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout8_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout9_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout9_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout9_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 293,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout8_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout8_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 294,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout8_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout8_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout8_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout8_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout8_9_PD",
"description": "Powerdown the clock group defined by 8 and 9.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout9_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout9_PD",
"description": "Powerdown SDCLKout8 and set to the state defined by SDCLKout8_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 295,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout9_POL",
"description": "Sets the polarity of clock on SDCLKout9 when device clock output is selected with SDCLKout9_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout9_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout8_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout8_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 296,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout10_11_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout10_11_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout10_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 8,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 297,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout10_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout10_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 299,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout10_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout10_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout10_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 300,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout10_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout11_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout11_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout11_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 301,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout10_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout10_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 302,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout10_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout10_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout10_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout10_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout10_11_PD",
"description": "Powerdown the clock group defined by 10 and 11.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout11_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout11_PD",
"description": "Powerdown SDCLKout10 and set to the state defined by SDCLKout10_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 303,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout11_POL",
"description": "Sets the polarity of clock on SDCLKout11 when device clock output is selected with SDCLKout11_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout11_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout10_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout10_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 304,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKout12_13_ODL",
"description": "Output drive level. Setting this bit increases the current to the CLKoutX_Y output buffers, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKout12_13_IDL",
"description": "Input drive level. Setting this bit increases the current to the clock distribution buffer sourcing CLKoutX_Y, which can slightly improve noise floor.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DCLKout12_DIV",
"description": "DCLKoutX_DIV sets the divide value for the clock output; the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1.",
"default": 2,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 305,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "DCLKout12_DDLY_CNTH",
"description": "Number of clock cycles the output is high when digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "DCLKout12_DDLY_CNTL",
"description": "Number of clock cycles the output is low when dynamic digital delay is engaged.",
"default": 5,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 307,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "DCLKout12_ADLY",
"description": "Device clock analog delay value. Delay step size is 25 ps. DCLKoutX_ADLY_PD = 0 (DCLK analog delay powered up) also adds a fixed 500-ps delay. Effective range is 500 ps to 1075 ps.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DCLKout12_ADLY_MUX",
"description": "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DUTY_CYCLE_CORRECTION",
"description": "Divided without duty cycle correction or half step. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "WITH_DUTY_CYCLE_CORRECTION",
"description": "Divided with duty cycle correction and half step."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "DCLKout12_MUX",
"description": "This selects the input to the device clock buffer.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDER_ONLY",
"description": "Divider Only. DCLKoutX_DIV = 1 is not valid when DCLKoutX_MUX = 0. DCLKoutX_DIV = 1 is valid for DCLKoutX_MUX = 1, or DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1."
},
{
"value": 1,
"name": "DIVIDER_WITH_DUTY_CYCLE_CORRECTION",
"description": "Divider with duty cycle Correction and half step"
},
{
"value": 2,
"name": "BYPASS",
"description": "Bypass"
},
{
"value": 3,
"name": "ANALOG_DELAY_AND_DIVIDER",
"description": "Analog delay + divider"
}
]
}
}
]
},
{
"addr": 308,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout12_HS",
"description": "Sets the device clock half step value. Half step must be zero (0) for a divide of 1.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SDCLKout13_MUX",
"description": "Sets the input the the SDCLKoutX outputs.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DEVICE_CLOCK_OUTPUT",
"description": "Device clock output"
},
{
"value": 1,
"name": "SYSREF_OUTPUT",
"description": "SYSREF output"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 1,
"name": "SDCLKout13_DDLY",
"description": "Sets the number of VCO cycles to delay the SDCLKout by",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout13_HS",
"description": "Sets the SYSREF clock half-step value.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ZERO_CYCLES",
"description": "0 cycles"
},
{
"value": 1,
"name": "MINUS_HALF_CYCLE",
"description": "-0.5 cycles"
}
]
}
}
]
},
{
"addr": 309,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SDCLKout12_ADLY_EN",
"description": "Enables analog delay for the SYSREF output",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "SDCLKout12_ADLY",
"description": "Sets the analog delay value for the SYSREF output. Step size is 150 ps, except first step (600 ps). SDCLKoutY_ADLY_EN = 1 (SDCLK analog delay enabled) also adds a fixed 700-ps delay. Effective range is 700 ps to 2950 ps.",
"default": 0,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 310,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DCLKout12_DDLY_PD",
"description": "Powerdown the device clock digital delay circuitry.",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DCLKout12_HSg_PD",
"description": "Powerdown the device clock glitchless half-step feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DCLKout12_ADLYg_PD",
"description": "Powerdown the device clock glitchless analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DCLKout12_ADLY_PD",
"description": "Powerdown the device clock analog delay feature.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKout12_13_PD",
"description": "Powerdown the clock group defined by 12 and 13.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "SDCLKout13_DIS_MODE",
"description": "Configures the output state of the SYSREF when disabled",
"default": 0,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "Active in normal operation"
},
{
"value": 1,
"name": "GLOBAL_PD_LOGIC_LOW",
"description": "If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active."
},
{
"value": 2,
"name": "GLOBAL_PD_LOGIC_HIGH",
"description": "If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage, otherwise it is active. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
},
{
"value": 3,
"name": "OUTPUT_NOMINAL_VCM_VOLTAGE",
"description": "Output is a nominal Vcm voltage. If LVPECL mode is used with emitter resistors to ground, the output Vcm is ~0 V, and each pin is ~0 V."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SDCLKout13_PD",
"description": "Powerdown SDCLKout12 and set to the state defined by SDCLKout12_DIS_MODE",
"default": 0,
"valid": {
"type": "enum",
"default": 1,
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 311,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SDCLKout13_POL",
"description": "Sets the polarity of clock on SDCLKout13 when device clock output is selected with SDCLKout13_MUX.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKout13_FMT",
"description": "Sets the output format of the SYSREF clocks",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DCLKout12_POL",
"description": "Sets the polarity of the device clocks from the DCLKoutX outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKout12_FMT",
"description": "Sets the output format of the device clocks.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 2,
"name": "HSDS_6_MA",
"description": "HSDS 6 mA"
},
{
"value": 3,
"name": "HSDS_8_MA",
"description": "HSDS 8 mA"
},
{
"value": 4,
"name": "HSDS_10_MA",
"description": "HSDS 10 mA"
},
{
"value": 5,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mV"
},
{
"value": 6,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mV"
},
{
"value": 7,
"name": "LCPECL",
"description": "LCPECL"
}
]
}
}
]
},
{
"addr": 312,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 5,
"name": "VCO_MUX",
"description": "Selects clock distribution path source from VCO0, VCO1, or CLKin (external VCO)",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "VCO_0",
"description": "VCO 0"
},
{
"value": 1,
"name": "VCO_1",
"description": "VCO 1"
},
{
"value": 2,
"name": "CLK_IN_1",
"description": "CLKin1 (external VCO)"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "OSCout_MUX",
"description": "Select the source for OSCout",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "BUFFERED_OSC_IN",
"description": "Buffered OSCin"
},
{
"value": 1,
"name": "FEEDBACK_MUX",
"description": "Feedback mux"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "OSCout_FMT",
"description": "Selects the output format of OSCout. When powered down, these pins may be used as CLKin2.",
"default": 4,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Powerdown (CLKin2)"
},
{
"value": 1,
"name": "LVDS",
"description": "LVDS"
},
{
"value": 4,
"name": "LVPECL_1_6_V",
"description": "LVPECL 1600 mVpp"
},
{
"value": 5,
"name": "LVPECL_2_0_V",
"description": "LVPECL 2000 mVpp"
},
{
"value": 6,
"name": "LVCMOS_NORM_INV",
"description": "LVCMOS (Norm / Inv)"
},
{
"value": 7,
"name": "LVCMOS_INV_NORM",
"description": "LVCMOS (Inv / Norm)"
},
{
"value": 8,
"name": "LVCMOS_NORM_NORM",
"description": "LVCMOS (Norm / Norm)"
},
{
"value": 9,
"name": "LVCMOS_INV_INV",
"description": "LVCMOS (Inv / Inv)"
},
{
"value": 10,
"name": "LVCMOS_OFF_NORM",
"description": "LVCMOS (Off / Norm)"
},
{
"value": 11,
"name": "LVCMOS_OFF_INV",
"description": "LVCMOS (Off / Inv)"
},
{
"value": 12,
"name": "LVCMOS_NORM_OFF",
"description": "LVCMOS (Norm / Off)"
},
{
"value": 13,
"name": "LVCMOS_INV_OFF",
"description": "LVCMOS (Inv / Off)"
},
{
"value": 14,
"name": "LVCMOS_OFF_OFF",
"description": "LVCMOS (Off / Off)"
}
]
}
}
]
},
{
"addr": 313,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "SYSREF_CLKin0_MUX",
"description": "Selects the SYSREF output from SYSREF_MUX or CLKin0 direct",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "SYSREF_MUX",
"description": "SYSREF Mux"
},
{
"value": 1,
"name": "CLK_IN_0",
"description": "CLKin0 direct (from CLKin0_OUT_MUX)"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "SYSREF_MUX",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL_SYNC",
"description": "Normal SYNC"
},
{
"value": 1,
"name": "RE_CLOCKED",
"description": "Re-clocked"
},
{
"value": 2,
"name": "SYSREF_PULSER",
"description": "SYSREF pulser"
},
{
"value": 3,
"name": "SYSREF_CONTINUOUS",
"description": "SYSREF continuous"
}
]
}
}
]
},
{
"addr": 314,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "SYSREF_DIV[12:8]",
"description": "SYSREF Divider MSBs",
"default": 12,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 315,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "SYSREF_DIV[7:0]",
"description": "SYSREF Divider LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 316,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "SYSREF_DDLY[12:8]",
"description": "These registers set the delay of the SYSREF digital delay value. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 317,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "SYSREF_DDLY[7:0]",
"description": "These registers set the delay of the SYSREF digital delay value. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 318,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "constant",
"end": 2,
"start": 2,
"value": 0
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "SYSREF_PULSE_CNT",
"description": "Sets the number of SYSREF pulses generated when not in continuous mode. See SYSREF_CLKin0_MUX, SYSREF_MUX for more information on SYSREF modes.",
"default": 3,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "PULSES_1",
"description": "1 pulse"
},
{
"value": 1,
"name": "PULSES_2",
"description": "2 pulse"
},
{
"value": 2,
"name": "PULSES_4",
"description": "4 pulse"
},
{
"value": 3,
"name": "PULSES_8",
"description": "8 pulse"
}
]
}
}
]
},
{
"addr": 319,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "PLL2_NCLK_MUX",
"description": "Selects the input to the PLL2 N divider",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "PLL_PRESCALER",
"description": "PLL prescaler"
},
{
"value": 1,
"name": "FEEDBACK_MUX",
"description": "Feedback mux"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "PLL1_NCLK_MUX",
"description": "Selects the input to the PLL1 N delay",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "OSC_IN",
"description": "OSCin"
},
{
"value": 1,
"name": "FEEDBACK_MUX",
"description": "Feedback mux"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 1,
"name": "FB_MUX",
"description": "When in zero-delay mode, the feedback mux selects the clock output to be fed back into the PLL1 N divider.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DCLK_OUT_6",
"description": "DCLKout6"
},
{
"value": 1,
"name": "DCLK_OUT_8",
"description": "DCLKout8"
},
{
"value": 2,
"name": "SYSREF_DIVIDER",
"description": "SYSREF Divider"
},
{
"value": 3,
"name": "EXTERNAL",
"description": "External"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "FB_MUX_EN",
"description": "When using zero-delay, FB_MUX_EN must be set to 1 to power up the feedback mux",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "POWERDOWN",
"description": "Feedback mux powered down"
},
{
"value": 1,
"name": "ENABLED",
"description": "Feedback mux enabled"
}
]
}
}
]
},
{
"addr": 320,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "PLL1_PD",
"description": "Powerdown PLL1",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "VCO_LDO_PD",
"description": "Powerdown VCO_LDO",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "VCO_PD",
"description": "Powerdown VCO",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "OSCin_PD",
"description": "Powerdown the OSCin port",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "SYSREF_GBL_PD",
"description": "Powerdown individual SYSREF outputs depending on the setting of SDCLKoutY_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows many SYSREF outputs to be controlled through a single bit.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "SYSREF_PD",
"description": "Powerdown the SYSREF circuitry and divider. If powered down, SYSREF output mode cannot be used. SYNC cannot be provided either.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "SYSREF_DDLY_PD",
"description": "Powerdown the SYSREF digital delay circuitry",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SYSREF_PLSR_PD",
"description": "Powerdown the SYSREF pulse generator.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
}
]
},
{
"addr": 321,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "DDLYd_SYSREF_EN",
"description": "Enables dynamic digital delay on SYSREF outputs",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "DDLYd12_EN",
"description": "Enables dynamic digital delay on DCLKout12",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "DDLYd10_EN",
"description": "Enables dynamic digital delay on DCLKout10",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "DDLYd7_EN",
"description": "Enables dynamic digital delay on DCLKout8",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "DDLYd6_EN",
"description": "Enables dynamic digital delay on DCLKout6",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "DDLYd4_EN",
"description": "Enables dynamic digital delay on DCLKout4",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "DDLYd2_EN",
"description": "Enables dynamic digital delay on DCLKout2",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "DDLYd0_EN",
"description": "Enables dynamic digital delay on DCLKout0",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
}
]
},
{
"addr": 322,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 0,
"name": "DDLYd_STEP_CNT",
"description": "Sets the number of dynamic digital delay adjustments that occur.",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 323,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SYSREF_CLR",
"description": "Resets and arms the SDCLKoutY_DDLY path, allowing local digital delays to take effect after a SYNC event. Except during the SYSREF setup procedure (see SYNC/SYSREF), this bit should always be programmed to 0. While this bit is set, extra current is used. Refer to Table 87.",
"default": 0,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "SYNC_1SHOT_EN",
"description": "SYNC one shot enables edge-sensitive SYNC.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "LEVEL_DETECTION",
"description": "SYNC is level sensitive and outputs are held in SYNC while SYNC is asserted."
},
{
"value": 1,
"name": "EDGE_DETECTION",
"description": "SYNC is edge sensitive, outputs are SYNCed on rising edge of SYNC. This results in the clock being held in SYNC for a minimum amount of time."
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SYNC_POL",
"description": "Sets the polarity of the SYNC pin.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal"
},
{
"value": 1,
"name": "INVERTED",
"description": "Inverted"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SYNC_EN",
"description": "Enables the SYNC functionality.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "SYNC_PLL2_DLD",
"description": "Assert SYNC until PLL2 DLD = 1",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "OFF",
"description": "Off"
},
{
"value": 1,
"name": "ASSERT_SYNC_UNTIL_PLL2_DLD",
"description": "Assert SYNC until PLL2 DLD = 1"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "SYNC_PLL1_DLD",
"description": "Assert SYNC until PLL1 DLD = 1",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "OFF",
"description": "Off"
},
{
"value": 1,
"name": "ASSERT_SYNC_UNTIL_PLL1_DLD",
"description": "Assert SYNC until PLL1 DLD = 1"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "SYNC_MODE",
"description": "Sets the method of generating a SYNC event.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_DLD_FLAGS_NO_SYNC",
"description": "Prevents SYNC pin, SYNC_PLL1_DLD flag, or SYNC_PLL2_DLD flag from generating a SYNC event."
},
{
"value": 1,
"name": "SYNC_FROM_PIN_OR_DLD_FLAG",
"description": "SYNC event generated from SYNC pin or, if enabled, the SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag"
},
{
"value": 2,
"name": "SYNC_PULSER_OR_PIN_OR_DLD_FLAG",
"description": "For use with pulser – SYNC/SYSREF pulses are generated by pulser block through the SYNC pin or, if enabled, the SYNC_PLL1_DLD flag or SYNC_PLL2_DLD flag."
},
{
"value": 3,
"name": "SYNC_WHEN_REGISTER_UPDATED",
"description": "For use with pulser – SYNC/SYSREF pulses are generated by pulser block when programming register 0x13E (SYSREF_PULSE_CNT) is written to (see SYSREF Pulser)."
}
]
}
}
]
},
{
"addr": 324,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "SYNC_DISSYSREF",
"description": "Prevents the SYSREF clocks from becoming synchronized during a SYNC event. If SYNC_DISSYSREF is enabled, it continues to operate normally during a SYNC event.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "SYNC_DIS12",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "SYNC_DIS10",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "SYNC_DIS8",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "SYNC_DIS6",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "SYNC_DIS4",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "SYNC_DIS2",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "SYNC_DIS0",
"description": "Prevents the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled, then it continues to operate normally during a SYNC event or SYSREF clock.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "SYNC/SYSREF Synchronization Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "SYNC/SYSREF Synchronization Disabled"
}
]
}
}
]
},
{
"addr": 325,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 1
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 1
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 1
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 1
},
{
"fieldtype": "constant",
"end": 2,
"start": 2,
"value": 1
},
{
"fieldtype": "constant",
"end": 1,
"start": 1,
"value": 1
},
{
"fieldtype": "constant",
"end": 0,
"start": 0,
"value": 1
}
]
},
{
"addr": 326,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "CLKin2_EN",
"description": "Enable CLKin2 to be used during auto-switching of CLKin_SEL_MODE.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED_FOR_AUTO_MODE",
"description": "Not enabled for auto mode"
},
{
"value": 1,
"name": "ENABLED_FOR_AUTO_MODE",
"description": "Enabled for auto mode"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "CLKin1_EN",
"description": "Enable CLKin1 to be used during auto-switching of CLKin_SEL_MODE.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED_FOR_AUTO_MODE",
"description": "Not enabled for auto mode"
},
{
"value": 1,
"name": "ENABLED_FOR_AUTO_MODE",
"description": "Enabled for auto mode"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "CLKin0_EN",
"description": "Enable CLKin0 to be used during auto-switching of CLKin_SEL_MODE.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED_FOR_AUTO_MODE",
"description": "Not enabled for auto mode"
},
{
"value": 1,
"name": "ENABLED_FOR_AUTO_MODE",
"description": "Enabled for auto mode"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "CLKin2_TYPE",
"description": "There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS. Bipolar is recommended for differential inputs such as LVDS or LVPECL. CMOS is recommended for DC-coupled single-ended inputs. When using bipolar, CLKinX and CLKinX* must be AC coupled. When using CMOS, CLKinX and CLKinX* may be AC or DC coupled if the input signal is differential. If the input signal is single-ended, the used input may be either AC or DC coupled, and the unused input must AC grounded (see Driving CLKin and OSCin Pins With a SingleEnded Source).",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "BIPOLAR",
"description": "Bipolar"
},
{
"value": 1,
"name": "MOS",
"description": "MOS"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "CLKin1_TYPE",
"description": "There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS. Bipolar is recommended for differential inputs such as LVDS or LVPECL. CMOS is recommended for DC-coupled single-ended inputs. When using bipolar, CLKinX and CLKinX* must be AC coupled. When using CMOS, CLKinX and CLKinX* may be AC or DC coupled if the input signal is differential. If the input signal is single-ended, the used input may be either AC or DC coupled, and the unused input must AC grounded (see Driving CLKin and OSCin Pins With a SingleEnded Source).",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NAME",
"description": "Descr"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "CLKin0_TYPE",
"description": "There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS. Bipolar is recommended for differential inputs such as LVDS or LVPECL. CMOS is recommended for DC-coupled single-ended inputs. When using bipolar, CLKinX and CLKinX* must be AC coupled. When using CMOS, CLKinX and CLKinX* may be AC or DC coupled if the input signal is differential. If the input signal is single-ended, the used input may be either AC or DC coupled, and the unused input must AC grounded (see Driving CLKin and OSCin Pins With a SingleEnded Source).",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NAME",
"description": "Descr"
}
]
}
}
]
},
{
"addr": 327,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 7,
"name": "CLKin_SEL_POL",
"description": "Inverts the CLKin polarity for use in pin select mode.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE_HIGH",
"description": "Active high."
},
{
"value": 1,
"name": "ACTIVE_LOW",
"description": "Active low."
}
]
}
},
{
"fieldtype": "normal",
"end": 6,
"start": 4,
"name": "CLKin_SEL_MODE",
"description": "Sets the mode used in determining the reference for PLL1.",
"default": 3,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "CLK_IN_0_MANUAL",
"description": "CLKin0 manual"
},
{
"value": 1,
"name": "CLK_IN_1_MANUAL",
"description": "CLKin1 manual"
},
{
"value": 2,
"name": "CLK_IN_2_MANUAL",
"description": "CLKin2 manual"
},
{
"value": 3,
"name": "PIN_SELECT_MODE",
"description": "Pin select mode"
},
{
"value": 4,
"name": "AUTO_MODE",
"description": "Auto mode"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 2,
"name": "CLKin1_OUT_MUX",
"description": "Selects where the output of the CLKin1 buffer is directed.",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "FIN",
"description": "Fin"
},
{
"value": 1,
"name": "FEEDBACK_MUX",
"description": "Feedback mux (zero-delay mode)"
},
{
"value": 2,
"name": "PLL1",
"description": "PLL1"
},
{
"value": 3,
"name": "OFF",
"description": "Off"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "CLKin0_OUT_MUX",
"description": "Selects where the output of the CLKin0 buffer is directed.",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "SYSREF_MUX",
"description": "SYSREF mux"
},
{
"value": 2,
"name": "PLL1",
"description": "PLL1"
},
{
"value": 3,
"name": "OFF",
"description": "Off"
}
]
}
}
]
},
{
"addr": 328,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 3,
"name": "CLKin_SEL0_MUX",
"description": "This set the output value of the CLKin_SEL0 pin. This register only applies if CLKin_SEL0_TYPE is set to an output mode",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "LOGIC_LOW",
"description": "Logic low"
},
{
"value": 1,
"name": "CLK_IN_0_LOS",
"description": "CLKin0 LOS"
},
{
"value": 2,
"name": "CLK_IN_0_SELECTED",
"description": "CLKin0 selected"
},
{
"value": 3,
"name": "DAC_LOCKED",
"description": "DAC locked"
},
{
"value": 4,
"name": "DAC_LOW",
"description": "DAC low"
},
{
"value": 5,
"name": "DAC_HIGH",
"description": "DAC high"
},
{
"value": 6,
"name": "SPI_READBACK",
"description": "SPI readback"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKin_SEL0_TYPE",
"description": "This sets the I/O type of the CLKin_SEL0 pin.",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "INPUT",
"description": "Input"
},
{
"value": 1,
"name": "INPUT_WITH_PULLUP",
"description": "Input with pull-up resistor"
},
{
"value": 2,
"name": "INPUT_WITH_PULLDOWN",
"description": "Input with pull-down resistor"
},
{
"value": 3,
"name": "OUTPUT",
"description": "Output (push-pull)"
},
{
"value": 4,
"name": "OUTPUT_INVERTED",
"description": "Output inverted (push-pull)"
},
{
"value": 6,
"name": "OUTPUT_OPEN_DRAIN",
"description": "Output (open drain)"
}
]
}
}
]
},
{
"addr": 329,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "SDIO_RDBK_TYPE",
"description": "Sets the SDIO pin to open drain when during SPI readback in 3-wire mode.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "OUTPUT_PUSH_PULL",
"description": "Output, push-pull"
},
{
"value": 1,
"name": "OUTPUT_OPEN_DRAIN",
"description": "Output, open-drain"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 3,
"name": "CLKin_SEL1_MUX",
"description": "This set the output value of the CLKin_SEL1 pin. This register only applies if CLKin_SEL1_TYPE is set to an output mode.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "LOGIC_LOW",
"description": "Logic low"
},
{
"value": 1,
"name": "CLK_IN_1_LOS",
"description": "CLKin1 LOS"
},
{
"value": 2,
"name": "CLK_IN_1_SELECTED",
"description": "CLKin1 selected"
},
{
"value": 3,
"name": "DAC_LOCKED",
"description": "DAC locked"
},
{
"value": 4,
"name": "DAC_LOW",
"description": "Logic low"
},
{
"value": 5,
"name": "DAC_HIGH",
"description": "DAC high"
},
{
"value": 6,
"name": "SPI_READBACK",
"description": "SPI readback"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "CLKin_SEL1_TYPE",
"description": "This sets the I/O type of the CLKin_SEL1 pin.",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "INPUT",
"description": "Input"
},
{
"value": 1,
"name": "INPUT_WITH_PULLUP",
"description": "Input with pull-up resistor"
},
{
"value": 2,
"name": "INPUT_WITH_PULLDOWN",
"description": "Input with pull-down resistor"
},
{
"value": 3,
"name": "OUTPUT",
"description": "Output (push-pull)"
},
{
"value": 4,
"name": "OUTPUT_INVERTED",
"description": "Output inverted (push-pull)"
},
{
"value": 6,
"name": "OUTPUT_OPEN_DRAIN",
"description": "Output (open drain)"
}
]
}
}
]
},
{
"addr": 330,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 3,
"name": "RESET_MUX",
"description": "This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an output mode.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "LOGIC_LOW",
"description": "Logic low"
},
{
"value": 2,
"name": "CLK_IN_2_SELECTED",
"description": "CLKin2 selected"
},
{
"value": 3,
"name": "DAC_LOCKED",
"description": "DAC locked"
},
{
"value": 4,
"name": "DAC_LOW",
"description": "Logic low"
},
{
"value": 5,
"name": "DAC_HIGH",
"description": "DAC high"
},
{
"value": 6,
"name": "SPI_READBACK",
"description": "SPI readback"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "RESET_TYPE",
"description": "This sets the I/O type of the RESET pin",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "INPUT",
"description": "Input"
},
{
"value": 1,
"name": "INPUT_WITH_PULLUP",
"description": "Input with pull-up resistor"
},
{
"value": 2,
"name": "INPUT_WITH_PULLDOWN",
"description": "Input with pull-down resistor"
},
{
"value": 3,
"name": "OUTPUT",
"description": "Output (push-pull)"
},
{
"value": 4,
"name": "OUTPUT_INVERTED",
"description": "Output inverted (push-pull)"
},
{
"value": 6,
"name": "OUTPUT_OPEN_DRAIN",
"description": "Output (open drain)"
}
]
}
}
]
},
{
"addr": 331,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 6,
"name": "LOS_TIMEOUT",
"description": "This controls the amount of time in which no activity on a CLKin forces a clock switch event.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "TIMEOUT_2700_NS",
"description": "370 kHz (2.7 µs)"
},
{
"value": 1,
"name": "TIMEOUT_480_NS",
"description": "2.1 MHz (480 ns)"
},
{
"value": 2,
"name": "TIMEOUT_115_NS",
"description": "8.8 MHz (115 ns)"
},
{
"value": 3,
"name": "TIMEOUT_45_NS",
"description": "22 MHz (45 ns)"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "LOS_EN",
"description": "Enables the LOS (loss-of-signal) timeout control. Valid only for MOS clock inputs. To ensure LOS is valid for AC-coupled inputs, no termination is allowed between CLKinX and CLKinX* pins unless DC-blocked. For example, 100-Ω termination across CLKin0 and CLKin0* pins on the IC side of AC coupling capacitors would invalidate the LOS detector. If termination is required, it should be placed on the other side of the AC coupling capacitors, away from the IC pins",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "TRACK_EN",
"description": "Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover mode. After device reset, tracking starts at DAC code = 512 (midrange). Tracking can be used to monitor PLL1 voltage in any mode.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled, only tracks when PLL1 is locked."
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "HOLDOVER_FORCE",
"description": "This bit forces holdover mode. When holdover mode is forced, if MAN_DAC_EN = 1, then the DAC sets the programmed MAN_DAC value. Otherwise the tracked DAC value sets the DAC voltage",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "MAN_DAC_EN",
"description": "This bit enables the manual DAC mode.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "MAN_DAC[9:8]",
"description": "Sets the value of the manual DAC when in manual DAC mode. MSBs",
"default": 2,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 332,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "MAN_DAC[7:0]",
"description": "Sets the value of the manual DAC when in manual DAC mode. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 333,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "DAC_TRIP_LOW",
"description": "Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled. Vtrip = (x + 1) * Vcc / 64",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 334,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 6,
"name": "DAC_CLK_MULT",
"description": "This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the DAC value is tracked.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "MULT_4",
"description": "4"
},
{
"value": 1,
"name": "MULT_64",
"description": "64"
},
{
"value": 2,
"name": "MULT_1024",
"description": "1024"
},
{
"value": 3,
"name": "MULT_16384",
"description": "16384"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "DAC_TRIP_HIGH",
"description": "Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is enabled. Vtrip = (x + 1) * Vcc / 64",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 335,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "DAC_CLK_CNTR",
"description": "This with DAC_CLK_MULT set the rate at which the DAC is updated. The update rate (in seconds) is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF (Hz)",
"default": 127,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 336,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "CLKin_OVERRIDE",
"description": "When CLKin_SEL_MODE = 0/1/2 to select a manual clock input, CLKin_OVERRIDE = 1 forces that clock input. Used with clock distribution mode for best performance.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal, no override"
},
{
"value": 1,
"name": "OVERRIDE",
"description": "Force select of only CLKin0/1/2, as specified by CLKin_SEL_MODE in manual mode"
}
]
}
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "HOLDOVER_PLL1_DET",
"description": "This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "PLL1_DLD_STICKY",
"description": "PLL1 DLD does not cause a clock switch event"
},
{
"value": 1,
"name": "PLL1_DLD_SWITCH",
"description": "PLL1 DLD causes a clock switch event"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "HOLDOVER_LOS_DET",
"description": "This enables HOLDOVER when PLL1 LOS signal is detected.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "HOLDOVER_VTUNE_DET",
"description": "Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "HOLDOVER_HITLESS_SWITCH",
"description": "Determines whether a clock switch event will enter holdover use hitless switching",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "HARD_SWITCH",
"description": "Hard switch"
},
{
"value": 1,
"name": "HITLESS_SWITCH",
"description": "Hitless switching (has an undefined switch time)"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "HOLDOVER_EN",
"description": "Sets whether holdover mode can be entered when holdover conditions are met.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
}
]
},
{
"addr": 337,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "HOLDOVER_DLD_CNT[13:8]",
"description": "The number of valid clocks of PLL1 PDF before holdover mode is exited. MSBs",
"default": 2,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 338,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "HOLDOVER_DLD_CNT[7:0]",
"description": "The number of valid clocks of PLL1 PDF before holdover mode is exited. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 339,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "CLKin0_R[13:8]",
"description": "The value of PLL1 R divider when CLKin0 is selected. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 340,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "CLKin0_R[7:0]",
"description": "The value of PLL1 R divider when CLKin0 is selected. LSBs",
"default": 120,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 341,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "CLKin1_R[13:8]",
"description": "The value of PLL1 R divider when CLKin1 is selected. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 342,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "CLKin1_R[7:0]",
"description": "The value of PLL1 R divider when CLKin1 is selected. LSBs",
"default": 150,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 343,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "CLKin2_R[13:8]",
"description": "The value of PLL1 R divider when CLKin2 is selected. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 344,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "CLKin2_R[7:0]",
"description": "The value of PLL1 R divider when CLKin2 is selected. LSBs",
"default": 150,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 345,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "PLL1_N[13:8]",
"description": "The value of PLL1 N divider. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 346,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL1_N[7:0]",
"description": "The value of PLL1 N divider. LSBs",
"default": 120,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 347,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 6,
"name": "PLL1_WND_SIZE",
"description": "PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase error between the reference and feedback of PLL1 is less than specified time, the PLL1 lock counter increments.",
"default": 3,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "WINDOW_4_NS",
"description": "Uses a 4 ns window."
},
{
"value": 1,
"name": "WINDOW_9_NS",
"description": "Uses a 9 ns window."
},
{
"value": 2,
"name": "WINDOW_19_NS",
"description": "Uses a 19 ns window."
},
{
"value": 3,
"name": "WINDOW_43_NS",
"description": "Uses a 43 ns window."
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "PLL1_CP_TRI",
"description": "This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ACTIVE",
"description": "PLL1 CPout1 is active"
},
{
"value": 1,
"name": "TRI_STATE",
"description": "PLL1 CPout1 is at TRI-STATE"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "PLL1_CP_POL",
"description": "PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope. A positive-slope VCXO increases output frequency with increasing voltage. A negativeslope VCXO decreases output frequency with increasing voltage.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NEGATIVE_SLOPE",
"description": "Negative-slope VCO/VCXO"
},
{
"value": 1,
"name": "POSITIVE_SLOPE",
"description": "Positive-slope VCO/VCXO"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "PLL1_CP_GAIN",
"description": "This field programs the PLL1 charge pump output current level. Iout = 50 µA + x * 100 µA",
"default": 4,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 348,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "PLL1_DLD_CNT[13:8]",
"description": "The reference and feedback of PLL1 must be within the window of phase error, as specified by PLL1_WND_SIZE for this many phase detector cycles, before PLL1 digital lock detect is asserted. MSBs",
"default": 32,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 349,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL1_DLD_CNT[7:0]",
"description": "The reference and feedback of PLL1 must be within the window of phase error, as specified by PLL1_WND_SIZE for this many phase detector cycles, before PLL1 digital lock detect is asserted. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 350,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 3,
"name": "PLL1_R_DLY",
"description": "Increasing delay of PLL1_R_DLY causes the outputs to lag from CLKinX. For use in zerodelay mode. Tdly = x * 205 ps",
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "PLL1_N_DLY",
"description": "Increasing delay of PLL1_N_DLY causes the outputs to lead from CLKinX. For use in zerodelay mode. Tdly = x * 205 ps",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 351,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "PLL1_LD_MUX",
"description": "This sets the output value of the Status_LD1 pin.",
"default": 1,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "LOGIC_LOW",
"description": "Logic low"
},
{
"value": 1,
"name": "PLL1_DLD",
"description": "PLL1 DLD"
},
{
"value": 2,
"name": "PLL2_DLD",
"description": "PLL2 DLD"
},
{
"value": 3,
"name": "PLL1_AND_PLL2_DLD",
"description": "PLL1 and PLL2 DLD"
},
{
"value": 4,
"name": "HOLDOVER_STATUS",
"description": "Holdover status"
},
{
"value": 5,
"name": "DAC_LOCKED",
"description": "DAC locked"
},
{
"value": 7,
"name": "SPI readback",
"description": "SPI readback"
},
{
"value": 8,
"name": "DAC_RAIL",
"description": "DAC rail"
},
{
"value": 9,
"name": "DAC_LOW",
"description": "DAC low"
},
{
"value": 10,
"name": "DAC_HIGH",
"description": "DAC high"
},
{
"value": 11,
"name": "PLL1_N",
"description": "PLL1_N"
},
{
"value": 12,
"name": "PLL1_N_2",
"description": "PLL1_N/2"
},
{
"value": 13,
"name": "PLL2_N",
"description": "PLL2_N"
},
{
"value": 14,
"name": "PLL2_N_2",
"description": "PLL2_N/2"
},
{
"value": 15,
"name": "PLL1_R",
"description": "PLL1_R"
},
{
"value": 16,
"name": "PLL1_R_2",
"description": "PLL1_R/2"
},
{
"value": 17,
"name": "PLL2_R",
"description": "PLL2_R"
},
{
"value": 18,
"name": "PLL2_R_2",
"description": "PLL2_R/2"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "PLL1_LD_TYPE",
"description": "Sets the I/O type of the Status_LD1 pin.",
"default": 6,
"valid": {
"type": "enum",
"values": [
{
"value": 3,
"name": "OUTPUT",
"description": "Output (push-pull)"
},
{
"value": 4,
"name": "OUTPUT_INVERTED",
"description": "Output inverted (push-pull)"
},
{
"value": 6,
"name": "OUTPUT_OPEN_DRAIN",
"description": "Output (open drain)"
}
]
}
}
]
},
{
"addr": 352,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "PLL2_R[11:8]",
"description": "Valid values for the PLL2 R divider. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 353,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL2_R[7:0]",
"description": "Valid values for the PLL2 R divider. LSBs",
"default": 2,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 354,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 5,
"name": "PLL2_P",
"description": "The PLL2 N prescaler divides the output of the VCO as selected by Mode_MUX1 and is connected to the PLL2 N divider.",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DIVIDE_8",
"description": "Divide by 8"
},
{
"value": 1,
"name": "DIVIDE_2",
"description": "Divide by 2"
},
{
"value": 2,
"name": "DIVIDE_2_2",
"description": "Divide by 2 (Second register ??, maybe it should be 1)"
},
{
"value": 3,
"name": "DIVIDE_3",
"description": "Divide by 3"
},
{
"value": 4,
"name": "DIVIDE_4",
"description": "Divide by 4"
},
{
"value": 5,
"name": "DIVIDE_5",
"description": "Divide by 5"
},
{
"value": 6,
"name": "DIVIDE_6",
"description": "Divide by 6"
},
{
"value": 7,
"name": "DIVIDE_7",
"description": "Divide by 7"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 2,
"name": "OSCin_FREQ",
"description": "The frequency of the PLL2 reference input to the PLL2 phase detector (OSCin/OSCin* port) must be programmed to support proper operation of the frequency calibration routine, which locks the internal VCO to the target frequency.",
"default": 4,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "FREQ_0_TO_63_MHZ",
"description": "0 to 63 MHz"
},
{
"value": 1,
"name": "FREQ_63_TO_127_MHZ",
"description": "63 to 127 MHz"
},
{
"value": 2,
"name": "FREQ_127_TO_255_MHZ",
"description": "127 to 255 MHz"
},
{
"value": 4,
"name": "FREQ_255_TO_500_MHZ",
"description": "255 to 500 MHz"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "PLL2_XTAL_EN",
"description": "If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be enabled with this bit to complete the oscillator circuit.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Oscillator amplifier disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Oscillator amplifier enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "PLL2_REF_2X_EN",
"description": "Enabling the PLL2 reference frequency doubler allows for higher phase-detector frequencies on PLL2 than would normally be allowed with the given VCXO or crystal frequency. Higher phase-detector frequencies reduce the PLL N values, which makes the design of wider-loop bandwidth filters possible.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Doubler disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Doubler enabled"
}
]
}
}
]
},
{
"addr": 355,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "constant",
"end": 2,
"start": 2,
"value": 0
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "PLL2_N_CAL[17:16]",
"description": "PLL2 never uses zero-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with the PLL2 prescaler during calibration for cascaded zero-delay mode. When calibration is complete, PLL2 uses the PLL2_N value. Cascaded zero-delay mode occurs when PLL2_NCLK_MUX = 1. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 356,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL2_N_CAL[15:8]",
"description": "PLL2 never uses zero-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with the PLL2 prescaler during calibration for cascaded zero-delay mode. When calibration is complete, PLL2 uses the PLL2_N value. Cascaded zero-delay mode occurs when PLL2_NCLK_MUX = 1. Mid bits",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 357,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL2_N_CAL[7:0]",
"description": "PLL2 never uses zero-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with the PLL2 prescaler during calibration for cascaded zero-delay mode. When calibration is complete, PLL2 uses the PLL2_N value. Cascaded zero-delay mode occurs when PLL2_NCLK_MUX = 1. LSBs",
"default": 12,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 358,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "PLL2_FCAL_DIS",
"description": "This disables the PLL2 frequency calibration on programming register 0x168.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "ENABLED",
"description": "Enabled"
},
{
"value": 1,
"name": "DISABLED",
"description": "Disabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 0,
"name": "PLL2_N[17:16]",
"description": "This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS = 0. MSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 359,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL2_N[15:8]",
"description": "This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS = 0. Mid bits",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 360,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL2_N[7:0]",
"description": "This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS = 0. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 361,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 5,
"name": "PLL2_WND_SIZE",
"description": "PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase error between the reference and feedback of PLL2 is less than the specified time, then the PLL2 lock counter increments. This value must be programmed to 2 (3.7 ns).",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 2,
"name": "WINDOW_SIZE_3_7_NS",
"description": "3.7 ns"
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 3,
"name": "PLL2_CP_GAIN",
"description": "This bit programs the PLL2 charge pump output current level. The table below also illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN.",
"default": 3,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "CHARGE_PUMP_CURRENT_100_UA",
"description": "100 µA"
},
{
"value": 1,
"name": "CHARGE_PUMP_CURRENT_400_UA",
"description": "400 µA"
},
{
"value": 2,
"name": "CHARGE_PUMP_CURRENT_1600_UA",
"description": "1600 µA"
},
{
"value": 3,
"name": "CHARGE_PUMP_CURRENT_3200_UA",
"description": "3200 µA"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "PLL2_CP_POL",
"description": "PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the negative charge pump polarity to be selected. Many VCOs use positive slope. A positive-slope VCO increases output frequency with increasing voltage. A negative-slope VCO decreases output frequency with increasing voltage.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NEGATIVE_SLOPE",
"description": "Negative-slope VCO/VCXO"
},
{
"value": 1,
"name": "POSITIVE_SLOPE",
"description": "Positive-slope VCO/VCXO"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "PLL2_CP_TRI",
"description": "PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "TRI_STATE",
"description": "TRI-State"
}
]
}
},
{
"fieldtype": "constant",
"end": 0,
"start": 0,
"value": 1
}
]
},
{
"addr": 362,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "SYSREF_REQ_EN",
"description": "Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for continuous pulses. When using this feature, enable the pulser and set SYSREF_MUX = 2 (pulser).",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "Disabled"
},
{
"value": 1,
"name": "ENABLED",
"description": "Enabled"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 0,
"name": "PLL2_DLD_CNT[15:8]",
"description": "The reference and feedback of PLL2 must be within the window of phase error, as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles, before PLL2 digital lock detect is asserted. MSBs",
"default": 32,
"valid": {
"type": "int"
}
}
]
},
{
"addr": 363,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "PLL2_DLD_CNT[7:0]",
"description": "The reference and feedback of PLL2 must be within the window of phase error, as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles, before PLL2 digital lock detect is asserted. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 364,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "normal",
"end": 5,
"start": 3,
"name": "PLL2_LF_R4",
"description": "Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop filters without requiring external components. Internal loop filter resistor R4 can be set according to the following table.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "RESISTANCE_200_OHM",
"description": "200 Ω"
},
{
"value": 1,
"name": "RESISTANCE_1000_OHM",
"description": "1 kΩ"
},
{
"value": 2,
"name": "RESISTANCE_2000_OHM",
"description": "2 kΩ"
},
{
"value": 3,
"name": "RESISTANCE_4000_OHM",
"description": "4 kΩ"
},
{
"value": 4,
"name": "RESISTANCE_16000_OHM",
"description": "16 kΩ"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "PLL2_LF_R3",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "RESISTANCE_200_OHM",
"description": "200 Ω"
},
{
"value": 1,
"name": "RESISTANCE_1000_OHM",
"description": "1 kΩ"
},
{
"value": 2,
"name": "RESISTANCE_2000_OHM",
"description": "2 kΩ"
},
{
"value": 3,
"name": "RESISTANCE_4000_OHM",
"description": "4 kΩ"
},
{
"value": 4,
"name": "RESISTANCE_16000_OHM",
"description": "16 kΩ"
}
]
}
}
]
},
{
"addr": 365,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 4,
"name": "PLL2_LF_C4",
"description": "Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop filters without requiring external components. Internal loop filter capacitor C4 can be set according to the following table",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "CAPACITANCE_10_PF",
"description": "10 pF"
},
{
"value": 1,
"name": "CAPACITANCE_15_PF",
"description": "15 pF"
},
{
"value": 2,
"name": "CAPACITANCE_29_PF",
"description": "29 pF"
},
{
"value": 3,
"name": "CAPACITANCE_34_PF",
"description": "34 pF"
},
{
"value": 4,
"name": "CAPACITANCE_47_PF",
"description": "47 pF"
},
{
"value": 5,
"name": "CAPACITANCE_52_PF",
"description": "52 pF"
},
{
"value": 6,
"name": "CAPACITANCE_66_PF",
"description": "66 pF"
},
{
"value": 7,
"name": "CAPACITANCE_71_PF",
"description": "71 pF"
},
{
"value": 8,
"name": "CAPACITANCE_103_PF",
"description": "103 pF"
},
{
"value": 9,
"name": "CAPACITANCE_108_PF",
"description": "108 pF"
},
{
"value": 10,
"name": "CAPACITANCE_122_PF",
"description": "122 pF"
},
{
"value": 11,
"name": "CAPACITANCE_126_PF",
"description": "126 pF"
},
{
"value": 12,
"name": "CAPACITANCE_141_PF",
"description": "141 pF"
},
{
"value": 13,
"name": "CAPACITANCE_146_PF",
"description": "146 pF"
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 0,
"name": "PLL2_LF_C3",
"description": "Internal loop filter components are available for PLL2, enabling either 3rd- or 4th-order loop filters without requiring external components. Internal loop filter capacitor C3 can be set according to the following table.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "CAPACITANCE_10_PF",
"description": "10 pF"
},
{
"value": 1,
"name": "CAPACITANCE_11_PF",
"description": "11 pF"
},
{
"value": 2,
"name": "CAPACITANCE_15_PF",
"description": "15 pF"
},
{
"value": 3,
"name": "CAPACITANCE_16_PF",
"description": "16 pF"
},
{
"value": 4,
"name": "CAPACITANCE_19_PF",
"description": "19 pF"
},
{
"value": 5,
"name": "CAPACITANCE_20_PF",
"description": "20 pF"
},
{
"value": 6,
"name": "CAPACITANCE_24_PF",
"description": "24 pF"
},
{
"value": 7,
"name": "CAPACITANCE_25_PF",
"description": "25 pF"
},
{
"value": 8,
"name": "CAPACITANCE_29_PF",
"description": "29 pF"
},
{
"value": 9,
"name": "CAPACITANCE_30_PF",
"description": "30 pF"
},
{
"value": 10,
"name": "CAPACITANCE_33_PF",
"description": "33 pF"
},
{
"value": 11,
"name": "CAPACITANCE_34_PF",
"description": "34 pF"
},
{
"value": 12,
"name": "CAPACITANCE_38_PF",
"description": "38 pF"
},
{
"value": 13,
"name": "CAPACITANCE_39_PF",
"description": "39 pF"
}
]
}
}
]
},
{
"addr": 366,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 3,
"name": "PLL2_LD_MUX",
"description": "This sets the output value of the Status_LD2 pin.",
"default": 2,
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "LOGIC_LOW",
"description": "Logic low"
},
{
"value": 1,
"name": "PLL1_DLD",
"description": "PLL1 DLD"
},
{
"value": 2,
"name": "PLL2_DLD",
"description": "PLL2 DLD"
},
{
"value": 3,
"name": "PLL1_AND_PLL2_DLD",
"description": "PLL1 and PLL2 DLD"
},
{
"value": 4,
"name": "HOLDOVER_STATUS",
"description": "Holdover status"
},
{
"value": 5,
"name": "DAC_LOCKED",
"description": "DAC locked"
},
{
"value": 7,
"name": "SPI readback",
"description": "SPI readback"
},
{
"value": 8,
"name": "DAC_RAIL",
"description": "DAC rail"
},
{
"value": 9,
"name": "DAC_LOW",
"description": "DAC low"
},
{
"value": 10,
"name": "DAC_HIGH",
"description": "DAC high"
},
{
"value": 11,
"name": "PLL1_N",
"description": "PLL1_N"
},
{
"value": 12,
"name": "PLL1_N_2",
"description": "PLL1_N/2"
},
{
"value": 13,
"name": "PLL2_N",
"description": "PLL2_N"
},
{
"value": 14,
"name": "PLL2_N_2",
"description": "PLL2_N/2"
},
{
"value": 15,
"name": "PLL1_R",
"description": "PLL1_R"
},
{
"value": 16,
"name": "PLL1_R_2",
"description": "PLL1_R/2"
},
{
"value": 17,
"name": "PLL2_R",
"description": "PLL2_R"
},
{
"value": 18,
"name": "PLL2_R_2",
"description": "PLL2_R/2"
}
]
}
},
{
"fieldtype": "normal",
"end": 2,
"start": 0,
"name": "PLL2_LD_TYPE",
"description": "Sets the I/O type of the Status_LD2 pin.",
"default": 6,
"valid": {
"type": "enum",
"values": [
{
"value": 3,
"name": "OUTPUT",
"description": "Output (push-pull)"
},
{
"value": 4,
"name": "OUTPUT_INVERTED",
"description": "Output inverted (push-pull)"
},
{
"value": 6,
"name": "OUTPUT_OPEN_DRAIN",
"description": "Output (open drain)"
}
]
}
}
]
},
{
"addr": 371,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "normal",
"end": 6,
"start": 6,
"name": "PLL2_PRE_PD",
"description": "Powerdown PLL2 prescaler",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "PLL2_PD",
"description": "Powerdown PLL2",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal operation"
},
{
"value": 1,
"name": "POWERDOWN",
"description": "Powerdown"
}
]
}
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "constant",
"end": 2,
"start": 2,
"value": 0
},
{
"fieldtype": "constant",
"end": 1,
"start": 1,
"value": 0
},
{
"fieldtype": "constant",
"end": 0,
"start": 0,
"value": 0
}
]
},
{
"addr": 380,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "OPT_REG_1",
"description": "This register must be written with the following value, depending on which LMK0482x family part is used to optimize VCO1 phase-noise performance over temperature. This register must be written before writing register 0x168 when using VCO1",
"valid": {
"type": "enum",
"values": [
{
"value": 21,
"name": "LMK04821_LMK04828",
"description": "LMK04821 or LMK04828"
},
{
"value": 24,
"name": "LMK04826",
"description": "LMK04826"
}
]
}
}
]
},
{
"addr": 381,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "OPT_REG_2",
"description": "This register must be written with the following value, depending on which LMK0482x family part is used to optimize VCO1 phase-noise performance over temperature. This register must be written before writing register 0x168 when using VCO1.",
"valid": {
"type": "enum",
"values": [
{
"value": 51,
"name": "LMK04821_LMK04828",
"description": "LMK04821 or LMK04828"
},
{
"value": 119,
"name": "LMK04826",
"description": "LMK04826"
}
]
}
}
]
},
{
"addr": 386,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "RB_PLL1_LD_LOST",
"description": "This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal state"
},
{
"value": 1,
"name": "DLD_EDGE_TRIGGERED",
"description": "This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "RB_PLL1_LD",
"description": "Read back register",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "PLL1_DLD_LOW",
"description": "PLL1 DLD is low"
},
{
"value": 1,
"name": "PLL1_DLD_HIGH",
"description": "PLL1 DLD is high"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "CLR_PLL1_LD_LOST",
"description": "To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "RB_PLL1_LD_LOST is set on next falling PLL1 DLD edge."
},
{
"value": 1,
"name": "RESET",
"description": "RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL1_LD_LOST to become set again"
}
]
}
}
]
},
{
"addr": 387,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "constant",
"end": 4,
"start": 4,
"value": 0
},
{
"fieldtype": "constant",
"end": 3,
"start": 3,
"value": 0
},
{
"fieldtype": "normal",
"end": 2,
"start": 2,
"name": "RB_PLL2_LD_LOST",
"description": "This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "Normal state"
},
{
"value": 1,
"name": "DLD_EDGE_TRIGGERED",
"description": "This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low"
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "RB_PLL2_LD",
"description": "PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid reading of this bit.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "PLL2_DLD_LOW",
"description": "PLL2 DLD is low"
},
{
"value": 1,
"name": "PLL2_DLD_HIGH",
"description": "PLL2 DLD is high"
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "CLR_PLL2_LD_LOST",
"description": "To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NORMAL",
"description": "RB_PLL2_LD_LOST is set on next falling PLL2 DLD edge."
},
{
"value": 1,
"name": "RESET",
"description": "RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL2_LD_LOST to become set again"
}
]
}
}
]
},
{
"addr": 388,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 6,
"name": "RB_DAC_VALUE[9:8]",
"description": "DAC value is 512 on power-on reset; if PLL1 locks upon power-up, the DAC value changes. MSBs",
"default": 2,
"valid": {
"type": "int"
}
},
{
"fieldtype": "normal",
"end": 5,
"start": 5,
"name": "RB_CLKin2_SEL",
"description": "This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NOT_SELECTED",
"description": "CLKin2 is not selected for input to PLL1."
},
{
"value": 1,
"name": "SELECTED",
"description": "CLKin2 is selected for input to PLL1."
}
]
}
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "RB_CLKin1_SEL",
"description": "This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NOT_SELECTED",
"description": "CLKin1 is not selected for input to PLL1."
},
{
"value": 1,
"name": "SELECTED",
"description": "CLKin1 is selected for input to PLL1."
}
]
}
},
{
"fieldtype": "normal",
"end": 3,
"start": 3,
"name": "RB_CLKin0_SEL",
"description": "This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NOT_SELECTED",
"description": "CLKin0 is not selected for input to PLL1."
},
{
"value": 1,
"name": "SELECTED",
"description": "CLKin0 is selected for input to PLL1."
}
]
}
},
{
"fieldtype": "normal",
"end": 1,
"start": 1,
"name": "RB_CLKin1_LOS",
"description": "This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "CLKin1 LOS is not active."
},
{
"value": 1,
"name": "ENABLED",
"description": "CLKin1 LOS is active."
}
]
}
},
{
"fieldtype": "normal",
"end": 0,
"start": 0,
"name": "RB_CLKin0_LOS",
"description": "This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "DISABLED",
"description": "CLKin0 LOS is not active."
},
{
"value": 1,
"name": "ENABLED",
"description": "CLKin0 LOS is active."
}
]
}
}
]
},
{
"addr": 389,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "RB_DAC_VALUE[7:0]",
"description": "DAC value is 512 on power-on reset; if PLL1 locks upon power-up, the DAC value changes. LSBs",
"valid": {
"type": "int"
}
}
]
},
{
"addr": 392,
"fields": [
{
"fieldtype": "constant",
"end": 7,
"start": 7,
"value": 0
},
{
"fieldtype": "constant",
"end": 6,
"start": 6,
"value": 0
},
{
"fieldtype": "constant",
"end": 5,
"start": 5,
"value": 0
},
{
"fieldtype": "normal",
"end": 4,
"start": 4,
"name": "RB_HOLDOVER",
"description": "",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "NO_HOLDOVER",
"description": "Not in HOLDOVER"
},
{
"value": 1,
"name": "HOLDOVER",
"description": "In HOLDOVER"
}
]
}
}
]
},
{
"addr": 8189,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "SPI_LOCK[23:16]",
"description": "Prevents SPI registers from being written to, except for 0x1FFD, 0x1FFE, and 0x1FFF. These registers must be written to sequentially and in order: 0x1FFD, 0x1FFE, 0x1FFF.",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "UNLOCKED",
"description": "Registers unlocked"
},
{
"value": 1,
"name": "LOCKED",
"description": "Registers locked"
}
]
}
}
]
},
{
"addr": 8190,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "SPI_LOCK[15:8]",
"description": "Prevents SPI registers from being written to, except for 0x1FFD, 0x1FFE, and 0x1FFF. These registers must be written to sequentially and in order: 0x1FFD, 0x1FFE, 0x1FFF. Mid bits",
"valid": {
"type": "enum",
"values": [
{
"value": 0,
"name": "UNLOCKED",
"description": "Registers unlocked"
},
{
"value": 1,
"name": "LOCKED",
"description": "Registers locked"
}
]
}
}
]
},
{
"addr": 8191,
"fields": [
{
"fieldtype": "normal",
"end": 7,
"start": 0,
"name": "SPI_LOCK[7:0]",
"description": "Prevents SPI registers from being written to, except for 0x1FFD, 0x1FFE, and 0x1FFF. These registers must be written to sequentially and in order: 0x1FFD, 0x1FFE, 0x1FFF. LSBs",
"default": 83,
"valid": {
"type": "enum",
"values": [
{
"value": 83,
"name": "UNLOCKED",
"description": "Registers unlocked"
},
{
"value": 0,
"name": "LOCKED",
"description": "Registers locked"
}
]
}
}
]
}
]
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment