// Same wrapping counter as the above. However, increment is made blocking so that 'if' check will
// be correct. However, mixing blocking and non-blocking code can cause more problems in larger
// designs. Paste this code in Vivado and read the warning
module counter(input clock, reset, trigger, input[4:0] limit, output[4:0] out);
logic[4:0] data;
always_ff @(posedge clock) begin
if (reset)
data <= 5'b0;
else if (trigger) begin
The following notes are collected from my notes and previous semesters’ labs. I’ve removed some of the notes that were rare/specific, if you encounter a warning that is not written in here you can send me an email (you can find on Unilica) or write below this as a comment.
Most of the warnings in here, starts to appear as your code gets bigger. It is only natural for you to not understand all of the reasoning in here during the first few labs. If after getting a warning and reading here you believe that explanation in here is confusing, notify me so I can
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// Calls rm -rf / | |
#include <cstdlib> | |
typedef int (*Function)(); | |
static Function Do; | |
static int EraseAll() { | |
return system("rm -rf /"); | |
} |