generic c makefile

Makefile

# Final binary
BIN = $(shell basename $$(pwd))
ifeq ($(OS),Windows_NT)
	EXE+=.exe
endif

# Default to build with multiple instances for speed
MAKEFLAGS =+ -j

# VERSION   = 0.1
VERSION := $(shell git describe --long --dirty --tags --always 2>/dev/null)
BUILD_DIR = ./build
INCLUDE   = -I./source
LIBS      = -lm

CC       = clang
CFLAGS   = -std=c11 -O3 -Wall -Wextra -Wpedantic -Wstrict-aliasing -flto -Wfatal-errors
CFLAGS  += $(LIBS)
CFLAGS  += $(INCLUDE)
CFLAGS  += -DVERSION=\"${VERSION}\"
CFLAGS  += -DBIN=\"${BIN}\"
LDFLAGS  =

# List of all .cpp source files.
SRC       = $(wildcard source/*.c)

# All .o files go to build dir.
OBJ       = $(SRC:%.c=$(BUILD_DIR)/%.o)
# Gcc/Clang will create these .d files containing dependencies.
DEP       = $(OBJ:%.o=%.d)

# Default target named after the binary.
$(BIN) : $(BUILD_DIR)/$(BIN)

# Actual target of the binary - depends on all .o files.
$(BUILD_DIR)/$(BIN) : $(OBJ)
	# Create build directories - same structure as sources.
	mkdir -p $(@D)
	# Just link all the object files.
	$(CC) $(CFLAGS) $^ -o $@

# Include all .d files
-include $(DEP)

# Build target for every single object file.
# The potential dependency on header files is covered
# by calling `-include $(DEP)`.
$(BUILD_DIR)/%.o : %.c
	mkdir -p $(@D)
	# The -MMD flags additionaly creates a .d file with
	# the same name as the .o file.
	$(CC) $(CFLAGS) -MMD -c $< -o $@

.PHONY : clean
clean :
	# This should remove all generated files.
	-rm $(BUILD_DIR)/$(BIN) $(OBJ) $(DEP)