Delta/sigma-DAC

dac.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 03/09/2024 02:08:14 PM
// Design Name: 
// Module Name: dac
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

// Ultra simple 2nd order sigma/delta DAC. 
// Heavily inspired by https://github.com/hamsternz/second_order_sigma_delta_DAC.
module dac(
    input dac_clk,
    input reset,
    input signed [13:0] data,
    output wire out
    );
    
    reg current_bit = 1'b0;
 
  reg signed [17:0] int1;
  reg signed [17:0] int2;
  reg signed [17:0] data_extended;
  
  wire [7:0] noise;
  random noise_gen(dac_clk, reset, 1'b1, noise); 
   
  assign out = current_bit;
    
  always @(posedge dac_clk or posedge reset)
    begin
      if (reset==1)
        begin
          int1<=14'd0;
          int2<=14'd0;
          current_bit <= 1'b0;
        end
      else
        begin
          data_extended = {data[13],data[13],data[13],data[13],data};
          if(current_bit == 1'b1)
            begin
              int1 = int1 + data_extended - (2**14);
              int2 = int2 + int1 - (2**13);
            end
          else
            begin
              int1 = int1 + data_extended + (2**14);
              int2 = int2 + int1 + (2**13) + noise[1:0];
            end
          current_bit = ~int2[17];
        end
    end
endmodule