vunit_axi_stream_master_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;

library vunit_lib;
context vunit_lib.vunit_context;
context vunit_lib.vc_context;

entity axi_stream_master_min_tb is
	generic(
		runner_cfg : string;
		tb_path    : string
	);
end entity axi_stream_master_min_tb;


architecture behaviour of axi_stream_master_min_tb is

	constant c_CLOCK_PERIOD : time    := 10 ns;
	constant c_DATAWIDTH    : natural := 32;

	constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(
		data_length => c_DATAWIDTH
	  );
	constant slave_axi_stream  : axi_stream_slave_t  := new_axi_stream_slave(
		data_length => c_DATAWIDTH
	);

	signal clk    : std_logic := '0';
	signal resetn : std_logic := '1';
	signal start  : std_logic := '0';
	signal done   : std_logic := '0';
	signal enable : std_logic := '0';

	-- master signals
	signal m_valid : std_logic;
	signal m_ready : std_logic;
	signal m_last  : std_logic;
	signal m_data  : std_logic_vector(c_DATAWIDTH-1 downto 0);

	-- slave signals
	signal s_valid : std_logic;
	signal s_ready : std_logic;
	signal s_last  : std_logic;
	signal s_data  : std_logic_vector(c_DATAWIDTH-1 downto 0);
begin
	------------------------
	-- entity instantiations
	------------------------

	axis_master: entity work.axi_stream_master_min
	generic map (
		DATA_WIDTH => c_DATAWIDTH
	)
	port map(
		aclk    => clk,
		aresetn => resetn,
		tvalid  => m_valid,
		tready  => m_ready,
		tdata   => m_data,
		tlast   => m_last,
		enable  => enable
	);

	axis_slave: entity vunit_lib.axi_stream_slave
	generic map(
		slave => slave_axi_stream
	)
	port map(
		aclk     => clk,
		areset_n => resetn,
		tvalid   => s_valid,
		tready   => s_ready,
		tdata    => s_data,
		tstrb    => "1111",
		tlast    => s_last
	);

	clock: process is
	begin
		clk <= not clk;
		wait for c_CLOCK_PERIOD/2;
	end process clock;

	main: process is
	begin
		test_runner_setup(runner, runner_cfg);
		while test_suite loop
			if run("test") then
				resetn <= '0';
				wait for 10*c_CLOCK_PERIOD;
				resetn <= '1';
				info("Init test");
				wait until rising_edge(clk);
				start <= '1';
				wait until rising_edge(clk);
				start <= '0';
				wait until rising_edge(clk);
				wait until done = '1';
				info("Test done");
			end if;
		  end loop;
		test_runner_cleanup(runner);
	end process main;

	master: process is
	begin
		wait until start = '1';
		wait until rising_edge(clk);

		info("Sending data...");
		enable <= '1';

		for i in 0 to 31 loop
			push_axi_stream(
				net,
				master_axi_stream,
				m_data,
				tlast => m_last
			);
		end loop;

		enable <= '0';
	end process master;


	slave: process is
		variable data : std_logic_vector(c_DATAWIDTH-1 downto 0);
		variable last : std_logic:='0';
	begin
		wait until start = '1';
		wait until rising_edge(clk);

		done <= '0';
		info("Receiving data...");

		for i in 0 to 31 loop
			pop_axi_stream(
				net,
				slave_axi_stream,
				tdata => data,
				tlast => last
			);
			info("slave data: (" & to_string(i)  & "): 0x" & to_hstring(data));
		end loop;

		wait until rising_edge(clk);
		done <= '1';
	end process slave;
end architecture behaviour;