Macro templates for creating assert functions in Verilog. (my original work)

easyAssertFuncs.v

`define NTB(name)\
        `"name``_tb`"

`define DEFASSERT(name,msb)\
        task assert_``name``;\
        input [``msb``:0] expected;\
        begin\
                if(expected !== ``name``_tb) begin\
                        $display("@E %03X %s Expected %X, got %X", story_tb, `NTB(name), expected, ``name``_tb);\
                        $stop;\
                end\
        end\
        endtask

`define DEFASSERT0(name)\
        task assert_``name``;\
        input expected;\
        begin\
                if(expected !== ``name``_tb) begin\
                        $display("@E %03X %s Expected %X, got %X", story_tb, `NTB(name), expected, ``name``_tb);\
                        $stop;\
                end\
        end\
        endtask