probe-rs Sequence that logs everything

log_sequence.rs

//! Example sequences that log things

use std::{
    sync::Arc,
    time::{Duration, Instant},
};

use probe_rs_target::CoreType;

use probe_rs::architecture::arm::ap::AccessPortError;
use probe_rs::architecture::arm::armv6m::{Aircr, Demcr};
use probe_rs::architecture::arm::component::TraceSink;
use probe_rs::architecture::arm::dp::{Ctrl, DpAddress, DpRegister};
use probe_rs::architecture::arm::memory::{ArmMemoryInterface, CoresightComponent};
use probe_rs::architecture::arm::sequences::{ArmDebugSequence, DebugEraseSequence};
use probe_rs::architecture::arm::{
    ApV2Address, ArmDebugInterface, ArmError, DapAccess, DapError, DapProbe,
    FullyQualifiedApAddress,
};
use probe_rs::{CoreType, MemoryMappedRegister};

#[derive(Debug)]
struct DefaultArmDebugSequence;
impl ArmDebugSequence for DefaultArmDebugSequence {}

/// Marker struct indicating initialization sequencing for logging parts.
#[derive(Debug)]
pub struct LogSequence {}

impl LogSequence {
    /// Create an example sequencer
    pub fn create() -> Arc<Self> {
        Arc::new(Self {})
    }
}

impl ArmDebugSequence for LogSequence {
    fn debug_port_setup(
        &self,
        interface: &mut dyn DapProbe,
        dp: DpAddress,
    ) -> Result<(), ArmError> {
        tracing::trace!(
            "debug_port_setup(interface: {}, {dp:x?})",
            interface.get_name()
        );
        DefaultArmDebugSequence
            .debug_port_setup(interface, dp)
            .inspect_err(|e| tracing::error!("Unable to setup debug port: {e}"))
    }
    
    fn reset_system(
        &self,
        core: &mut dyn ArmMemoryInterface,
        core_type: probe_rs::CoreType,
        debug_base: Option<u64>,
    ) -> Result<(), ArmError> {
        tracing::trace!("reset_system(interface, {core_type:?}, {debug_base:x?})");
        DefaultArmDebugSequence
            .reset_system(core, core_type, debug_base)
            .inspect_err(|e| tracing::error!("Unable to reset system: {e}"))
    }


    fn allowed_access_ports(&self) -> Vec<u8> {
        tracing::trace!("allowed_access_ports()");
        DefaultArmDebugSequence.allowed_access_ports()
    }

    fn debug_port_connect(
        &self,
        interface: &mut dyn DapProbe,
        dp: DpAddress,
    ) -> Result<(), ArmError> {
        tracing::trace!(
            "debug_port_connect(interface: {}, {dp:x?})",
            interface.get_name()
        );
        DefaultArmDebugSequence.debug_port_connect(interface, dp)
    }

    fn debug_port_start(
        &self,
        interface: &mut dyn DapAccess,
        dp: DpAddress,
    ) -> Result<(), ArmError> {
        tracing::trace!("debug_port_start(interface, {dp:x?})");
        DefaultArmDebugSequence
            .debug_port_start(interface, dp)
            .inspect_err(|e| tracing::error!("Unable to start debug port: {e}"))
    }
    
    fn debug_core_start(
        &self,
        interface: &mut dyn ArmDebugInterface,
        core_ap: &FullyQualifiedApAddress,
        core_type: CoreType,
        debug_base: Option<u64>,
        cti_base: Option<u64>,
    ) -> Result<(), ArmError> {
        tracing::trace!(
            "debug_core_start(interface, {core_ap:x?}, {core_type:?}, {debug_base:08x?}, {cti_base:08x?})"
        );
        DefaultArmDebugSequence
            .debug_core_start(interface, core_ap, core_type, debug_base, cti_base)
            .inspect_err(|e| tracing::error!("Unable to start debug core: {e}"))
    }

    fn debug_core_stop(
        &self,
        interface: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
    ) -> Result<(), ArmError> {
        tracing::trace!("debug_core_stop(interface, {core_type:?})");
        DefaultArmDebugSequence.debug_core_stop(interface, core_type)
    }

    fn debug_device_unlock(
        &self,
        interface: &mut dyn ArmDebugInterface,
        default_ap: &FullyQualifiedApAddress,
        permissions: &Permissions,
    ) -> Result<(), ArmError> {
        tracing::trace!("debug_device_unlock(interface, {default_ap:?}, {permissions:?})");
        DefaultArmDebugSequence.debug_device_unlock(interface, default_ap, permissions)
    }

    fn debug_erase_sequence(&self) -> Option<Arc<dyn DebugEraseSequence>> {
        tracing::trace!("debug_erase_sequence()");
        DefaultArmDebugSequence.debug_erase_sequence()
    }

    fn debug_port_stop(&self, interface: &mut dyn DapProbe, dp: DpAddress) -> Result<(), ArmError> {
        tracing::trace!(
            "debug_port_stop(interface: {}, {dp:x?})",
            interface.get_name()
        );
        DefaultArmDebugSequence.debug_port_stop(interface, dp)
    }

    fn prepare_running_on_ram(
        &self,
        vector_table_addr: u64,
        session: &mut Session,
    ) -> Result<(), Error> {
        tracing::trace!("prepare_running_on_ram({vector_table_addr:08x}, session)");
        DefaultArmDebugSequence.prepare_running_on_ram(vector_table_addr, session)
    }

    fn recover_support_start(
        &self,
        interface: &mut dyn ArmMemoryInterface,
    ) -> Result<(), ArmError> {
        tracing::trace!("recover_support_start(interface)");
        DefaultArmDebugSequence.recover_support_start(interface)
    }

    fn reset_catch_set(
        &self,
        core: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
        debug_base: Option<u64>,
    ) -> Result<(), ArmError> {
        tracing::trace!("reset_catch_set(core, {core_type:?}, {debug_base:08x?})");
        DefaultArmDebugSequence.reset_catch_set(core, core_type, debug_base)
    }

    fn reset_hardware_assert(&self, interface: &mut dyn DapProbe) -> Result<(), ArmError> {
        tracing::trace!("reset_hardware_assert(interface: {})", interface.get_name());
        DefaultArmDebugSequence.reset_hardware_assert(interface)
    }

    fn reset_hardware_deassert(
        &self,
        probe: &mut dyn ArmDebugInterface,
        default_ap: &FullyQualifiedApAddress,
    ) -> Result<(), ArmError> {
        tracing::trace!("reset_hardware_deassert(probe, {default_ap:x?})");
        DefaultArmDebugSequence.reset_hardware_deassert(probe, default_ap)
    }

    fn trace_start(
        &self,
        interface: &mut dyn ArmDebugInterface,
        components: &[CoresightComponent],
        sink: &TraceSink,
    ) -> Result<(), ArmError> {
        tracing::trace!("trace_start()");
        DefaultArmDebugSequence.trace_start(interface, components, sink)
    }

    fn reset_catch_clear(
        &self,
        core: &mut dyn ArmMemoryInterface,
        core_type: CoreType,
        debug_base: Option<u64>,
    ) -> Result<(), ArmError> {
        tracing::trace!("reset_catch_clear(core, {core_type:?}, {debug_base:08x?})");
        DefaultArmDebugSequence.reset_catch_clear(core, core_type, debug_base)
    }
}